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commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 1 march, 2010 idtcv183-1a idtcv183-2a commercial temperature range programmable flexpc clock the idt logo is a registered trademark of integrated device technology, inc. ? 2010 integrated device technology, inc. dsc 7030/4 features: ? compliant with intel ck505 gen ii spec ? one high precision pll for cpu, ssc and n programming ? one high precision pll for src, ssc and n programming ? one high precision pll for sata/pci, and ssc ? one high precision pll for 96mhz/48mhz ? push-pull ios for differential outputs ? support spread spectrum modulation, ?0.5 down spread and others ? support smbus block read/write, byte read/write ? available in tssop package functional block diagram key features ? internal serial resistor can be enabled by smbus control register b19b7 to save the board space and material cost ? direct cpu and src clock frequency programming?write the hex number into byte [16:18], 1 mhz stepping. ? linear and smooth transition for the cpu and src frequency programming. ? four power on hardware modes ? see page 6, cfg configu- ration table 2. ? cv183-1 ? when cfg[1:0] = 11, sata clock power on default is from 48/96 mhz fixed pll. ? cv183-2 ? when cfg[1:0] = 11, sata clock power on default is from src pll. outputs: ? 2*0.7v differential cpu clk pair ? 10*0.7v differential src clk pair ? one cpu_itp/src differential clock pair ? one src0/dot96 differential clock pair ? 6*pci, 33.3mhz ? 1*48mhz ? 1*ref ? 1*sata key specifications: ? cpu/src clk cycle to cycle jitter < 85ps ? pci clk cycle to cycle jitter < 500ps ? all src, src[0:11] phase noise < 3.10s rms, pcie gen ii ? src3, 4, 6, 7, designated pcie gen ii outputs, nominal interpair skew = 0 ps not recommended for new designs. the last time buy date for this product is 5/19/2011. please refer to pdn k-10-18. sata/src2 sm bus controller control logic 48mhz/96mhz output buffer sdata sclk ckpwrgd/pd# fsc,b,a 48mhz dot96/src0 fixed pll pll2 xtal osc amp cpu output buffer stop logic xtal_in xtal_out cpu[1:0] pll1 ssc n programmable src5_en, tme cr_[h:a]# cpu_stop# pci_stop# itp_en pll3 ssc pll4 ssc n programmable src clk output buffer stop logic src clk output buffer stop logic src1/se src[7:3], [11:9] pci[4:0], pcif5 cpu_itp/src8 ref pci/sata
commercial temperature range 2 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor pin configuration tssop top view 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 scl sda fsb/test_mode xtal_in xtal_out v dd _ref cpuc0 v ss _cpu cput0 srcc6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 srct3/cr#_c pci0/cr#_a pci3/cfgp v ss _pci usb_48/fsa v dd _io dot96t/srct0 v ss _48mhz srct1/se1 dot96c/srcc0 srcc8/cpu_itpc v dd _pll3 v dd _48mhz v dd _pll3_io ref/fsc/test_sel ckpwrgd/pd# v dd _cpu cpuc1 29 30 31 32 v dd _pci pci1/cr#_b pcif5/itp_en pci4/src5_en v ss _io srcc1/se2 v ss _pll3 satat/srct2 satac/srcc2 v ss _src srcc3/cr#_d v dd _src_io srct4 srcc4 v ss _src srct9 srcc9 srcc11/cr#_g v ss _ref cput1 v dd _cpu_io io_v out srct8/cpu_itpt v dd _src_io srct7/cr#_f srct6 srcc7/cr#_e v ss _src srct11/cr#_h v dd _src pci_stop#/srct5 srcc10 srct10 cpu_stop#/srcc5 v dd _src_io pci2/tme
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 3 pin description pin # name type description 1 pci0/cr#_a i/o 33.33mhz. src0, 2 differential clock output enable, control src0 and src2, 0 = enable. mode is selected by smbus control register. default is pci clock mode. 2v dd _pci pwr 3.3v 3 pci1/cr#_b i/o 33.33mhz. src1, 4 differential clock output enable, control src1 and src4, 0 = enable. mode is selected by smbus control register. default is pci clock mode. 4 pci2/tme i/o 33.33mhz. trust mode enable. high = overclocking disabled. power-on latch. 5 pci3/cfgp out 33.33mhz. clock configuration bit, combined with pin 4 (see cfg table), power on latch 6 pci4/src5_en i/o 33.33mhz. pin 37, 38 mode selection. power on latch, high = src5, low = cpu and pci stop#. 7 pcif5/itp_en i/o 33.33mhz. pin 46, 47 mode selection. power on latch, high = cpu_itp, low = src8. 8v ss _pci gnd gnd 9v dd _48 pwr 3.3v 10 usb 48/fs_a i/o 48mhz, frequency select, power on latch 11 v ss _48 gnd gnd 12 v dd _io pwr 0.8v 13 srct0/dot96t out differential output clock. src or dot96. mode selected by smbus control register, default is src0. 14 srcc0/dot96c out differential output clock. src or dot96. mode selected by smbus control register, default is src0. 15 v ss _io gnd gnd 16 v dd _pll3 pwr 3.3v 17 srct1/se1 out differential or single end clock output. mode selected by smbus control register. default is src1. 18 srcc1/se2 out differential or single end clock output. mode selected by smbus control register. default is src1. 19 v ss _pll3 gnd gnd 20 v dd _pll3_io pwr 0.8v 21 satat/srct2 out differential output clock 22 satac/srcc2 out differential output clock 23 v ss _src gnd gnd 24 srct3/cr#_c i/o src clock. src differential clock output enable, control src0 and src2, 0 = enable. mode selected by smbus control register. default is src3. 25 srcc3/cr#_d i/o src clock. src d ifferential clock output enable, control src1 and src4, 0 = enable. mode selected by smbus control register. default is src3. 26 v dd _src_io pwr 0.8v 27 srct4 out differential output clock 28 srcc4 out differential output clock 29 v ss _src gnd gnd 30 srct9 out differential output clock 31 srcc9 out differential output clock 32 srcc11/cr#_g i/o src clock. src differential clock output enable, control src9, 0 = enable. mode selected by smbus control register. default is src11. 33 srct11/cr#_h i/o src clock. src differential clock output enable, control src10, 0 = enable. mode selected by smbus control register. default is src11. 34 srct10 out differential output clock 35 srcc10 out differential output clock 36 v dd _src_io pwr 0.8v 37 cpu_stop#/srcc5 i/o cpu stop, low = stop. src clock. mode selected by pin6, src5_en. 38 pci_stop#/srct5 i/o pci stop, low = stop. src clock. mode selected by pin6, src5_en. 39 v dd _src pwr 3.3v 40 srcc6 out differential output clock 41 srct6 out differential output clock 42 v ss _src gnd gnd
commercial temperature range 4 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor pin # name type description 43 srcc7/cr#_e i/o src clock. src differential clock output enable, control src6, 0 = enable. mode selected by smbus control register. default is src7. 44 srct7/cr#_f i/o src clock. src differential clock output enable, control src8, 0 = enable. mode selected by smbus control register. default is src7. 45 v dd _src_io pwr 0.8v 46 srcc8/cpu_ itpc out src clock. cpu clock. mode selected by pin7. 47 srct8/cpu_ itpt out src clock. cpu clock. mode selected by pin7. 48 io_v out out v_io adjustment 49 v dd _cpu_io pwr 0.8v 50 cpuc1 out differential output clock 51 cput1 out differential output clock 52 v ss _cpu gnd gnd 53 cpuc0 out differential output clock 54 cput0 out differential output clock 55 v dd _cpu pwr 3.3v 56 ckpwrgd/pd# in ckpwrgd power good, active low, used to latch fsa,b,c, itp_en, tme, and src5_en , active high. after, becomes power down, low active. 57 fs_b/testmode i n frequency select at ckpwrgd assertion. test mode selection, see test_mode selection table.q 58 v ss _ref gnd gnd 59 xtal_out out xtal out 60 xtal_in in xtal in 61 v dd _ref pwr 3.3v 62 ref/fs_c/testsel i/o 14.318mhz. frequency select at ckpwrgd assertion. selects test mode if pulled above 2v at ckpwrgd assertion. 63 sda i/o smbus clock 64 scl in smbus data pin description, continued frequency selection fsc, b, a cpu src[7:0] pci usb dot ref 101 100 100 33.3 48 96 14.318 001 133 100 33.3 48 96 14.318 011 166 100 33.3 48 96 14.318 010 200 100 33.3 48 96 14.318 000 266 100 33.3 48 96 14.318 100 333 100 33.3 48 96 14.318 110 400 100 33.3 48 96 14.318 111 reserve 100 33.3 48 96 14.318 test mode selection (1) if test_sel sampled above 2v at ckpwrgd active low test_mode cpu src pci/f ref dot_96/dot_ssc usb 1 ref/n ref/n ref/n ref ref/n ref/n 0 hi-z hi-z hi-z hi-z hi-z hi-z note: 1. once test clock operation has been invoked, test_mode pin will select between the hi-z and ref/n, with v ih _fs and v il _fs thresholds.
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 5 index block write protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20-27 8 master byte count, n (0 is not valid) 28 1 slave ack (acknowledge) 29-36 8 master first data byte (offset data byte) 37 1 slave ack (acknowledge) 38-45 8 master 2nd data byte 46 1 slave ack (acknowledge) : master nth data byte slave acknowledge master stop index block read protocol master can stop reading any time by issuing the stop bit without waiting until nth byte (byte count bit 30-37). symbol description min max unit v dda 3.3v core supply voltage 4.6 v v dd 3.3v logic input supply voltage gnd - 0.5 4.6 v t stg storage temperature ?65 +150 c t ambient ambient operating temperature 0 +70 c t case case temperature +115 c esd prot input esd protection 2000 v human body model absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. sm protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20 1 master repeated start 21-28 8 master d3h 29 1 slave ack (acknowledge) 30-37 8 slave byte count, n (block read back of n bytes) 38 1 master ack (acknowledge) 39-46 8 slave first data byte (offset data byte) 47 1 master ack (acknowledge) 48-55 8 slave 2nd data byte ack (acknowledge) : master ack (acknowledge) slave nth data byte not acknowledge master stop
commercial temperature range 6 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor cfgp (pin5) voltage decoding table cfg configuration table 1 cfg configuration table 2 cfg1, cfg0 byte11 bit[7:6] low, 0 0, 0 1 low, 1 0, 0 0 mid, 0 0, 1 1 mid, 1 0, 1 0 high, 0 1, 0 1 high, 1 1, 1 1 cfgp, tme (pin5, pin4) n programming enable byte16 bit 3 state min typ max low 0v 0.55v 0.9v mid 1.3v 1.65v 2v high 2.4v 2.75v vdd sata (pin21, 22) 00 pll1 (1) pll4 src (1) pll4 (from src pll) (1) cfb table (default src) pll4 (1) pll2 (3) 01 pll1 (1) pll3 (1) pll3 (1) cfb table (default src) pll4 (1) pll2 (3) 10 pll1 (2) pll3 (1) pll3 (1) cfb table (default src) pll4 (1) pll2 (3) 11 pll1 (2) pll2 (cv183-1) (3) pll4 (cv183-2) (1) pll4 (1) pin17 = 25mhz, pll2 pin18 = 1394a, pll3 (3) pll4 (1) pll2 (3) n o t e: 1. ssc 0.5% dow n spread 2. ssc 0.5% denter spread 3. no ssc src 48/96 cfg[1: 0] cpu pci pin17/ 18
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 7 cfb table (pin 17-18) id3,id2,id1,id0 comments 0000 ck505 56 pin tssop ck505 yc 0001 ck505 64 pin tssop ck505 yc 0010 48 pin qfn ck505 yc 0011 56 pin qfn ck505 yc 0100 64 pin qfn ck505 yc 0101 72 pin qfn ck505 yc 0110 48 pin ssop ck505 yc 0111 56 pin ssop ck505 yc 1000 reserved ck505 derivative (non yc) 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved device id table 000 0.3v 001 0.4v 010 0.5v 011 0.6v 100 0.7v 101 0.8v 110 0.9v 111 1v io_vout [2:0] table cfb[3,2,1,0] b1b[4:1] pin17, 18 0000 src (pll4) 0001 src (pll4) 0010 100mhz 0.5% ssc (pll3) 0011 100mhz 1.0% ssc (pll3) 0100 100mhz 1.5% ssc (pll3) 0101 100mhz 2.0% ssc (pll3) 110 100mhz 2.5% ssc (pll3) 0111 reserved 1000 1394a 3.3v, ssc off byte4 bit0 lose control 1001 1394a&b 3.3v, ssc off byte4 bit0 lose control 1010 1394b 3.3v, ssc off byte4 bit0 lose control 1011 27mhz, 3.3v, byte4 bit0 control the ssc enable, byte1 bit5 control the down/center 1100 25mhz 3.3v, ssc off byte4 bit0 lose control 1101 pin17 = 25mhz, pll2 pin18 = 1394a, pll3 both no ssc 1110 reserved 1111 reserved sata/pci from pll3 or pll4 (see cfg table) comments from pll3, pin17 = 1394a, pin18 = 1394b, sata/pci from pll4 default, sata/pci from pll3 or pll4 (see cfg table) from pll3 , sata/pci from pll4 from pll3 , sata/pci from pll4 from pll3 , sata/pci from pll4 reserved reserved from pll3 , sata/pci from pll4 from pll3 , sata/pci from pll4 25mhz from pll2 1394 from pll3, sata/pci from pll4 from pll3 , sata/pci from pll4 from pll3 , sata/pci from pll4 from pll3 , sata/pci from pll4 from pll3 , sata/pci from pll4 from pll3 , sata/pci from pll4
commercial temperature range 8 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor byte 2 bit output(s) affected description/function 0 1 type power on 7 ref output enable tristate enable rw 1 6 usb_48 output enable tristate enable rw 1 5 pcif5 output enable tristate enable rw 1 4 pci4 output enable tristate enable rw 1 3 pci3 output enable tristate enable rw 1 2 pci2 output enable tristate enable rw 1 1 pci1 output enable tristate enable rw 1 0 pci0 output enable tristate enable rw 1 control registers byte 0 notes: 1. sticky 1, can only be reset by power off. byte 1 ? byte 16 bit 3 has to be "1". this bit will decode the power on latched value of pins 4, 5 (see cfg table 1). n-programming procedure . ? user writes the desired cpu frequency in hex form into cpun [8:0], byte 16, 17. ? user writes the desired src frequency in hex form into pn [7:0], byte 18. bit output(s) affected description/function 0 1 type power on 7 fsc latched fsc r latched value 6 fsb latched fsb r latched value 5 fsa latched fsa r latched value 4 iamt_en iamt mode legacy mode enabled rw hw m1 setting(1) 3 reserved rw 0 2 cfb table enable enable cfb table disable cfb table (pin 17, 18 is src) rw 0 1 sata source normal, depend on cfb and cgf table pll2 rw 0 0 pd_restore smbus control re g isters setting after the power down power on default, with some exceptions save register contents rw 1 bit output(s) affected description/function 0 1 type power on 7 src0_sel pin13/14 mode select src0 dot96 rw 0 6 pll1_ssc_dc ssc mode selection down spread center spread rw 0 5 pll3_ssc_dc ssc mode selection down spread center spread rw 0 4 pll3_cfb3 rw 0 3 pll3_cfb2 only valid if byte0 bit2 = 0 rw 0 2 pll3_cfb1 see pll3_cfb table, rw 0 1 pll3_cfb0 configure pin17, 18 output mode rw 1 0 pci reflect pci pll status pll3 pll4 r
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 9 bit output(s) affected description/function 0 1 type power on 7 src11 output enable tristate enabled rw 1 6 src10 output enable tristate enabled rw 1 5 src9 output enable tristate enabled rw 1 4 src8/itp output enable tristate enabled rw 1 3 src7 output enable tristate enabled rw 1 2 src6 output enable tristate enabled rw 1 1 src5 output enable tristate enabled rw 1 0 src4 output enable tristate enabled rw 1 byte 3 byte 4 bit output(s) affected description/function 0 1 type power on 7 src3 output enable di sabled enabled rw 1 6 sata/src2 output enable di sabled enabled rw 1 5 src1 output enable di sabled enabled rw 1 4 src0/dot96 output enable di sabled enabled rw 1 3 cpu1 output enable di sabled enabled rw 1 2 cpu0 output enable di sabled enabled rw 1 1 pll1_ssc_on ssc enable di sabled enabled rw 1 0 pll3_ssc_on ssc enable di sabled enabled rw 1 byte 5 bit output(s) affected description/function 0 1 type power on 7 cr#_a pin1 mode selection pci0 mode cr#_a mode rw 0 6 cr#_a control cr#_a control selection src0 src2 rw 0 5 cr#_b pin3 mode selection pci1mode cr#_b mode rw 0 4 cr#_b control cr#_b control selection src1 (1) src4 rw 0 3 cr#_c pin24 mode selection srct3 mode cr#_c mode rw 0 2 cr#_c control cr#_c control selection src0 src2 rw 0 1 cr#_d pin25 mode selection srcc3 mode cr#_d mode rw 0 0 cr#_d control cr#_d control selection src1 src4 rw 0 note: 1. only when src1 is src clock.
commercial temperature range 10 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor byte 9 bit output(s) affected description / function 0 1 type power on 7 pcif5 with pci_stop# free running free runni ng stoppable rw 0 6 tme_strap tme pin 4 power on latch read back normal no overclocking r 5 ref drive strength strength control 1x 2x rw 1 4 only valid when byte9 bit3 is 1 hi-z ref/n mode rw 0 3 test mode entry control normal operation test mode, controlled rw 0 by byte9 bit 4 2 io_vout2 rw 1 1 io_vout1 programmable io_v out voltage rw 0 0 io_vout0 rw 1 byte 6 (1) bit output(s) affected description/function 0 1 type power on 7 cr#_e pin43 mode selection, control src6 srcc7 mode cr#_e mode, control src 6 rw 0 6 cr#_f pin44 mode selection, control src8 srct7 mode cr#_f mode, control src 8 rw 0 5 cr#_g pin32 mode selection, control src9 src c11 mode cr#_g mode, control src 9 rw 0 4 cr#_h pin33 mode selection, control src10 srct11 mode cr#_h mode, control src 10 rw 0 3 reserved rw 0 2 reserved rw 0 1 sscd_stp_crtl if set, sscd stop with pci_stop# free running stoppable rw 0 0 src_stp_crtl if set, srcs stop with pci_stop# free running stoppable rw 0 note: 1. stop - cput and srct stay high, cpuc and srcc stay low. bit output(s) affected description / function 0 1 type power on 7 device_id3 r 6 device_id2 see device id table r 5 device_id1 r 4 device_id0 r 3 rw 0 2 rw 0 1 se1_oe output enable disabled enabled rw 1 0 se2_oe output enable disabled enabled rw 1 byte 8 byte 7 bit output(s) affected description / function 0 1 type power on 7 revision id 1 6 revision id 0 5 revision id 0 4 revision id 1 3 vendor id 0 2 vendor id 1 1 vendor id 0 0 vendor id 1
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 11 byte 11 byte 14 reserved byte 13 bit output(s) affected description / function 0 1 type power on 7 48m strength control 1 1.2 rw 1 6 ref strength control 1 1.2 rw 1 5 pcif5 strength control 1 1.2 rw 0 4 pci4 strength control 1 1.2 rw 0 3 pci3 strength control 1 1.2 rw 0 2 pci2 strength control 1 1.2 rw 0 1 pci1 strength control 1 1.2 rw 0 0 pci0 strength control 1 1.2 rw 0 bit output(s) affected description/ function 0 1 type power on 7 src5_en_strap r the latch of src5_en 6 pll3 pll3 enable pll3 pwr dwn pwr up rw 1 5 pll2 pll2 enable pll2 pwr dwn pwr up rw 1 4 src_div src divider disable disable enable rw 1 3 pci_div pci divider disable disable enable rw 1 2 cpu_div cpu divider disable disable enable rw 1 1 cpu1 free run controlled by cpu_stp# free run controllable rw 1 0 cpu0 free run controlled by cpu_stp# free run controllable rw 1 byte 10 byte 12 - byte count - default 0x13h bit output(s) affected description/ function 0 1 type power on 7cfg1 r see cfg table 1, 2 6cfg0 r see cfg table 1, 2 525mhz-en 25mhz disabled in pd/ m1 (for both pll3 and pll2 25mhz) disabled enabled (can not be reset by pd restore at power down) rw 0 4 reserved rw 1 3cpu_itp_amt en m1 mode clk enable at m1 mode only if itp_en = 1 disable enable rw 0 2 cpu1_amt_en m1 mode clk enable at m1 mode disable enable rw 1 1 pci gen ii gen ii compliance none gen ii gen ii r 1 0 cpu_itp_stop en free run control free run controlled rw 1
commercial temperature range 12 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor byte 16 byte 15, watch dog (1) bit output(s) affected description / function 0 1 type power on 7 watch dog enable watch dog alarm enable disabled enabled rw 0 6 watch dog select watch dog hard/soft alarm select hard alarm only hard and soft alarm rw 0 5 watch dog hard alarm status watch dog hard alarm status normal alarm r 4 watch dog soft alarm status watch dog soft alarm status normal alarm r 3 watch dog control watch dog time base control 290ms base 1160ms base rw 0 2 wd_1_ timer 2 watchdog_1_alarm timer rw 1 1 wd_1_ timer 1 default is 7*290ms rw 1 0 wd_1_ timer 0 rw 1 note: 1. hard alarm switch to hw fs frequency. byte 17 (pll1) bit output(s) affected description / function 0 1 type power on 7wdeapd set byte15 bit7 = 1 after power down to enable the watch dog after the power down disabled enabled rw 0 6 27mhz ssc1 see 27mhz ssc table rw 0 5 27mhz ssc0 see 27mhz ssc table rw 0 4 test _scl on chip test mode enable normal sclk=1, clk outputs = 1 sclk=0, clk outputs=0 rw 0 3 n programming see cfg table 1 disabled enabled rw power on latch 2 reserved rw 0 1 reserved rw 0 0cpun8 rwfs latch bit output(s) affected description / function 0 1 type power on 7 cpun7 rw 6 cpun6 rw 5 cpun5 rw 4 cpun4 rw 3 cpun3 rw 2 cpun2 rw 1 cpun1 rw 0 cpun0 rw fs latch cpu clock frequency = cpun [8:0] (hex) 27mhz ssc1, ssc0 spread (byte1 bit5 control center or down spread) 00 0.5% 01 1.0% 10 1.5% 11 2.0% 27mhz ssc table
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 13 byte 18 (pll3) bit output(s) affected description / function 0 1 type power on 7pn 7 rw 6pn 6 rw 5 pn 5 src clock frequency = rw 4 pn 4 pnc [7:0] rw 100mhz 3 pn 3 (hex) rw 2pn 2 rw 1pn 1 rw 0pn 0 rw bit output(s) affected description / function 0 1 type power on 7 output serial resistor 0 ohm (external resistor needed) 33 ohm (no external resistor needed) rw 0 6 pll1 ssc 0.45%(p-p) rw 0 5 pll3 ssc 0.45%(p-p) rw 0 4 pll4 ssc 0.45%(p-p) rw 0 3 pll4_ssc_dc ssc mode selection down spread centered at 99.75mhz center spread rw 0 2 reserved rw 0 1 reserved rw 0 0 reserved rw 0 spread % selection 0.5% (p-p) byte 19 clock source selection, written after stop bit bit out p ut ( s ) affected descri p tion/ function 0 1 t yp epower on 7 don?t change the default rw 1 6 don?t change the default rw 0 5 don?t change the default rw 0 4 don?t change the default rw 0 3 don?t change the default rw 0 2 don?t change the default rw 0 1 pll4 (src) ssc on/off control disable enable rw 1 0 don?t change the default rw 0 byte 30
commercial temperature range 14 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor absolute maximum ratings electrical characteristics - input/supply/common output parameters parameter symbol conditions min max units notes ambient operating temp tambient - 0 70 c 1 supply voltage vddxxx supply voltage 3.135 3.465 v 1 supply voltage vddxxx_io low-voltage differential i/o supply 0.70 0.88 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 o utput high voltage v ohs e single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v ols e single-ended outputs, i ol = 1 ma 0.4 v 1 o utput high voltage v ohdif differential outputs, i oh = tbd ma 0.7 0.9 v 1 output low voltage v oldif differential o utputs , i ol = tbd ma 0.4 v 1 low threshold input- high voltage (test mode) v ih_fs_test 3.3 v +/-5% 2 v dd + 0.3 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating supply current i dd_dp 3.3v supply, pll3 off 140 ma 1 i dd_io 0.8v supply, differential io current, all outputs enabled 30 ma 1 i dd_pd3.3 3.3v supply, power down mode 5 ma 1 i dd_pdio 0.8v io supply, power down mode 0 ma 1 i dd_iamt3.3 3.3v supply, iamt mode 30 ma 1 i dd_iamt0.8 0.8v io supply, iamtmode 10 ma 1 input frequency f i v dd = 3.3 v 14.31818 mhz 2 pin inductance l p in 7nh1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins tbd pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 power down current iamt mode current input capacitance parameter symbol conditions min max units notes maximum supply voltage vddxxx supply voltage 4.6 v 1,7 maximum supply voltage vdd xxx_io low-volt age differential i/o supply 3.8 v 1,7 maximum input voltage v ih 3.3v lvcmos inputs 4.6 v 1,7,8 minimum input voltage v il any input gnd - 0.5 v 1,7 storage temperature ts - -65 150 c 1,7 input esd protection esd prot human body model 2000 v 1,7
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 15 ac electrical characteristics - input/common parameters ac electrical characteristics - low power differential outputs electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,6 33.33mhz output nominal 30.00900 ns 6 33.33mhz output spread 30.15980 ns 6 absolute min/max period t abs 33.33mhz output nominal/spread 29.49100 30.65980 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 %1 skew t skew v t = 1.5 v 250 ps 1 intentional pci-pci delay t delay v t = 1.5 v ps 1,9 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 output high current i oh output low current i ol 29.99100 t period 200 nominal clock period parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 2.5 5 v/ns 1,2 falling edge slew rate t flr differential measurement 2.5 5 v/ns 1,2 slew rate variation t slvar single-ended measurement 20 % 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 cpu[1:0] skew cpu skew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpu skew20 differential measurement 150 ps 1 src[10:0] skew src skew differential measurement 250 ps 1,10 parameter symbol conditions min max units notes clk stabilization t stab from vdd power-up or de-assertion of pd# to 1st clock 1.8 ms 1 tdrive_src t drsrc src output enable after pci_stop# de-assertion 15 ns 1 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns 1 tfall_pd# t fall 5ns1 trise_pd# t ri se 5ns1 fall/rise time of pd#, pci_stop# and cpu_stop# inputs
commercial temperature range 16 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor electrical characteristics - usb48mhz electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v olsmb @ i pullup 0.4 v 1 current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1 parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t period 48.00mhz output nominal 20.83125 20.83542 ns 2 absolute min/max period t abs 48.00mhz output nominal 20.48130 21.18540 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 %1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 350 ps 1 output high current i oh i ol output low current
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 17 electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t period 14.318mhz output nominal 69.8203 69.8622 ns 2 absolute min/max period t abs 14.318mhz output nominal 69.8203 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1 notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# fa lling) 6 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 10 src 3,4,6,7, are 0 ps nominal interpair skew 5 defined as the total variation of all crossing voltages of clk rising and clk# fa lling. matching applies to rising edge rate of clk and fa lling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#. 7 operation under these conditions is neither implied, nor guaranteed. 9 see pci clock-to-clock delay figure 8 maximum input voltage is not to exceed maximum vdd
commercial temperature range 18 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor pci_stop# assertion (transition from ?1? to ?0?) pci_stop# - de-assertion (transition from '0' to '1') pci_stop# pcif5 33mhz pci[4:0] 33mhz src 100mhz src# 100mhz t su pci_stop# pcif5 33mhz pci[4:0] 33mhz src 100mhz src# 100mhz t su t drive_src pci stop functionality pci_stop# src src# pci 1 normal normal 33mhz 0 high low low
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 19 cpu stop functionality the cpu_stop# signal is an active low input controlling the cpu outputs. this signal can be asserted asynchronously. cpu_stop# assertion (transition from ?1? to ?0?) asserting cpu_stop# pin stops all cpu outputs that are set to be stoppable after their next transition. when the smbus cpu_stop tri-state bit corresponding to the cpu output of interest is programmed to a ?0?, cpu output will stop cpu_true = high and cpu_complement = low. when the s mbus cpu_stop# tri-state bit corresponding to the cpu output of interest is programmed to a ?1?, cpu outputs will be tri-stated. cpu_stop# - de-assertion (transition from ?0? to ?1?) with the de-assertion of cpu_stop# all stopped cpu outputs will resume without a glitch. the maximum latency from the de-assert ion to active outputs is two to six cpu clock periods. if the control register tristate bit corresponding to the output of interest is programmed to ?1?, then the stopped cpu outputs will be driven high within 10ns of cpu_stop# de-assertion to a voltage greater than 200mv. cpu_stop# cpu cpu# cpu_stop# cpu cpu# cpu internal t drive _cpu_stop 10ns > 200mv cpu_stop# cpu cpu# 1 normal normal 0 high low
commercial temperature range 20 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor pd# assertion pd# cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 pd# de-assertion pd# cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 t stable <1.8ms
commercial temperature range idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor 21 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 pcclockhelp @idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa--0.10--.004 variations min max min max 64 16.90 17.10 .665 .673 10-0039 n d mm. d (inch) reference doc.: jedec publication 95, mo-153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions index area index area 12 1 n d e1 e sea ting plane sea ting plane a1 a a2 e -c- -c- b c l aaa c tssop package dimensions ordering information part / order number shipping packaging package temperature cv183-1 apag t ubes 64-pin tssop 0 to +70c cv183-1apag8 tape and reel 64-pin tssop 0 to +70c cv183-2 apag t ubes 64-pin tssop 0 to +70c CV183-2APAG8 tape and reel 64-pin tssop 0 to +70c "g" after the two-letter package code are the pb-free configuration and are rohs compliant. "a" is the device revision designator (will not correlate to the datasheet revision)
commercial temperature range 22 idtcv183-1 / idtcv183-2 programmable flexpc clock for p4 processor november 07, 2006 fw initial release. january 15, 2007 fw updated datasheet. january 17, 2007 fw removed resolution table pg 5, updated byte 12 pg 11. january 22, 2007 fw updated cfg configuration table 2. march 16, 2007 fw added 64-pin package dimensions (page, 22). march 28, 2007 fw updated cfg configuration table 2 (page 6). added byte 30 (page 13). november 2, 2009 rdw changed vddio min spec from 0.72 to 0.70 v. march 3, 2010 rdw removed pvg package code revision history march 17, 2010 rdw added missing idd numbers updated ordering information moved to final

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